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PHK04P02T
P-channel vertical D-MOS logic level FET
Rev. 02 -- 14 December 2010 Product data sheet
1. Product profile
1.1 General description
Logic level P-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using vertical D-MOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Suitable for high frequency applications due to fast switching characteristics Suitable for logic level gate drive sources Suitable for very low gate drive sources voltage
1.3 Applications
Battery powered applications High-speed digital interfaces
1.4 Quick reference data
Table 1. Symbol VDS ID Ptot Quick reference data Parameter drain-source voltage drain current total power dissipation drain-source on-state resistance VGS = -2.5 V; ID = -1 A; Tj = 25 C VGS = -4.5 V; ID = -1 A; Tj = 25 C VGS = -4.5 V; ID = -1 A; VDS = -10 V; Tj = 25 C Conditions Tj 25 C; Tj 150 C Tsp = 25 C Min Typ Max Unit -16 -4.6 6 5 V A W
Static characteristics RDSon 117 80 150 120 m m nC
Dynamic characteristics QGD gate-drain charge 1.83 -
NXP Semiconductors
PHK04P02T
P-channel vertical D-MOS logic level FET
2. Pinning information
Table 2. Pin 1 2 3 4 5 6 7 8 Pinning information Symbol Description S S S G D D D D source source source gate drain drain drain drain
1 4 S
001aaa025
Simplified outline
8 5
Graphic symbol
D
G
SOT96-1 (SO8)
3. Ordering information
Table 3. Ordering information Package Name PHK04P02T SO8 Description plastic small outline package; 8 leads; body width 3.9 mm Version SOT96-1 Type number
4. Limiting values
Table 4. Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tsp = 25 C Tsp = 25 C; pulsed; tp 5 s Tsp = 100 C Tsp = 25 C Tsp = 25 C; pulsed Tsp = 25 C Tsp = 100 C Conditions Tj 25 C; Tj 150 C RGS = 20 k Min -8 -55 -55 Max -16 -16 8 -1.87 -4.66 -26.4 5 2 150 150 -4.66 -26 Unit V V V A A A W W C C A A
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
PHK04P02T
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 14 December 2010
2 of 12
NXP Semiconductors
PHK04P02T
P-channel vertical D-MOS logic level FET
100 Ptot (%) 80
001aam073
120 ID (%) 80
001aam074
60
40 40 20
0 0 40 80 120 Ta (C) 160
0 0 40 80 120 Ta (C) 160
VGS -10 V Fig 1. Normalised power dissipation as a function of ambient temperature
102 IDM (A) 10
Fig 2.
Normalized continuous drain current as a function of ambient temperature
001aam075
RDS(on) = VDS / ID
tp = 1 ms 10 ms 100 ms
1 D.C. 10-1
10-2 10-1
1
10 VDS (V)
102
Tsp = 25 C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHK04P02T
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 14 December 2010
3 of 12
NXP Semiconductors
PHK04P02T
P-channel vertical D-MOS logic level FET
5. Thermal characteristics
Table 5. Symbol Rth(j-sp) Thermal characteristics Parameter thermal resistance from junction to solder point Conditions mounted on metal clad substrate Min Typ 25 Max Unit K/W
102 Zth(j-sp) (K/W) 10
001aam076
D = 0.5 0.2 0.1 0.05 0.02
P = tp T
1 10-1 10-2 10-3
single pulse 10-5 10-4 10-3 10-2
tp T
t
10-6
10-1
1
10 tp (s)
Fig 4.
Transient thermal impedance from junction to solder point as a function of pulse duration
PHK04P02T
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 14 December 2010
4 of 12
NXP Semiconductors
PHK04P02T
P-channel vertical D-MOS logic level FET
6. Characteristics
Table 6. Symbol V(BR)DSS VGS(th) IDSS IGSS RDSon Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage drain leakage current gate leakage current drain-source on-state resistance Conditions ID = -10 A; VGS = 0 V; Tj = 25 C ID = -1 mA; VDS = VGS; Tj = 25 C ID = -1 mA; VDS = VGS; Tj = 150 C VDS = -13 V; VGS = 0 V; Tj = 25 C VDS = -13 V; VGS = 0 V; Tj = 150 C VGS = 8 V; VDS = 0 V; Tj = 25 C VGS = -8 V; VDS = 0 V; Tj = 25 C VGS = -2.5 V; ID = -1 A; Tj = 25 C VGS = -2.5 V; ID = -1 A; Tj = 150 C VGS = -1.8 V; ID = -0.5 A; Tj = 25 C VGS = -4.5 V; ID = -1 A; Tj = 25 C Dynamic characteristics QG(tot) QGS QGD Ciss Coss Crss td(on) tr td(off) tf gfs VSD trr Qr total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time transfer conductance source-drain voltage reverse recovery time recovered charge VDS = -13 V; ID = -1 A; Tj = 25 C IS = -0.62 A; VGS = 0 V; Tj = 25 C IS = -0.5 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = -12.8 V; Tj = 25 C VDS = -10 V; RL = 10 ; VGS = -8 V; RG(ext) = 6 ; Tj = 25 C; ID = -1 A VDS = -13 V; VGS = 0 V; f = 1 MHz; Tj = 25 C ID = -1 A; VDS = -10 V; VGS = -4.5 V; Tj = 25 C 1.5 7.2 1.7 1.83 528 200 57 2 4.5 45 20 4.5 -0.62 75 69 -1.3 nC nC nC pF pF pF ns ns ns ns S V ns nC Min -16 -0.4 -0.1 Typ -0.6 -50 -13 10 10 117 175 140 80 Max -100 -100 100 100 150 230 180 120 Unit V V V nA A nA nA m m m m
Static characteristics
Source-drain diode
PHK04P02T
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 14 December 2010
5 of 12
NXP Semiconductors
PHK04P02T
P-channel vertical D-MOS logic level FET
-5 ID (A) -4 -3 -2 -1 0 0
001aam077
-4.5 -2.5 -1.8
0.7 RDS(on) -0.8 -1.0 -1.2 () 0.6 -0.9 -1.1 0.5 0.4 0.3 0.2 0.1 0 0 -1 -2 -3 -1.8 -2.5 -4.5
001aam078
-1.3 -1.2 -1.1 -1.0 -0.9 VGS (V) = -0.8
VGS (V) = -1.3
-0.5
-1.0
-1.5
VDS (V)
-2.0
-4
ID (A)
-5
Tj = 25 C Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values
001aam079
Tj = 25 C Fig 6. Drain-source on-state resistance as a function of drain current; typical values
8 gfs (S) 6 Tj = 150 C
001aam080
-5 ID (A) -4 -3
Tj = 25 C
Tj = 150 C
Tj = 25 C
4 -2 -1 0 0 2
-0.5
-1.0
-1.5
VGS (V)
-2.0
0 0
-0.8
-1.6
ID (A)
-2.4
VDS > ID x RDSon Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values
1.6 a 1.4 VGS = -4.5 V 1.2 -1.8 V 0.4 1.0 0.2 -2.5 V
001aam081
VDS > ID x RDSon Fig 8. Forward transconductance as a function of drain current; typical values
0.8 VGS(th) (V) 0.6 typical
001aam082
minimum
0.8
0.6 0 50 100 Tj (C) 150
0 0 50 100 Tj (C) 150
ID = 1 mA; VDS = VGS
Fig 9.
Normalized drain-source on-state resistance factor as a function of junction temperature
Fig 10. Gate-source threshold voltage as a function of junction temperature
(c) NXP B.V. 2010. All rights reserved.
PHK04P02T
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 02 -- 14 December 2010
6 of 12
NXP Semiconductors
PHK04P02T
P-channel vertical D-MOS logic level FET
10-2 ID (A) 10-3 10-4
001aam083
103
001aam084
C (pF)
Ciss
Coss 102
10-5 10-6 10-7 -1.0
Crss
-0.8
-0.6
-0.4
-0.2 0 VGS (V)
10 -10-1
-1
-10
VDS (V)
-102
VDS = -5 V; Tj = 25 C Fig 11. Sub-threshold drain current as a function of gate-source voltage
VGS = 0 V; f = 1 MHz Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
5 IF (A) 4
001aam086
-5 VGS (V) -4 -3 -2 -1 0 0 2 4 6
001aam085
3 Tj = 150 C Tj = 25 C
2
1
0 8 10 QG (nC) 0 0.4 0.8 VSDS (V) 1.2
Tj = 25 C; ID = -1 A Fig 13. Gate-source voltage as a function of turn-on gate charge; typical values
VGS = 0 V Fig 14. Reverse diode current as a function of reverse diode voltage; typical values
PHK04P02T
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 14 December 2010
7 of 12
NXP Semiconductors
PHK04P02T
P-channel vertical D-MOS logic level FET
7. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c y HE vMA
Z
8 5
Q A2 A1 pin 1 index Lp
1 4
(A 3)
A
L wM detail X
e
bp
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
o
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8 o 0
Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-18
Fig 15. Package outline SOT96-1 (SO8)
PHK04P02T All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 14 December 2010
8 of 12
NXP Semiconductors
PHK04P02T
P-channel vertical D-MOS logic level FET
8. Revision history
Table 7. Revision history Release date 20101214 Data sheet status Product data sheet Change notice Supersedes PHK04P02T v.1 Document ID PHK04P02T v.2 Modifications:
* *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Product specification -
PHK04P02T v.1
20020501
PHK04P02T
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 14 December 2010
9 of 12
NXP Semiconductors
PHK04P02T
P-channel vertical D-MOS logic level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective
9.3
Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
PHK04P02T
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 14 December 2010
10 of 12
NXP Semiconductors
PHK04P02T
P-channel vertical D-MOS logic level FET
product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, IC-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE -- are trademarks of NXP B.V. HD Radio and HD Radio logo -- are trademarks of iBiquity Digital Corporation.
10. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PHK04P02T
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 14 December 2010
11 of 12
NXP Semiconductors
PHK04P02T
P-channel vertical D-MOS logic level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . .9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . . 11
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 December 2010 Document identifier: PHK04P02T

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